Hardware-Accelerated BNN on FPGA

This project was originally conceived by my batchmate Harsha Kaushalya, who led the effort to build a hardware-accelerated neural network entirely from scratch on a Nexys A7 FPGA. I collaborated on the project alongside Imal Adhikari, focusing primarily on the embedded systems and hardware side of the implementation.

The goal was ambitious: train a neural network in software, then implement its inference logic directly in hardware, bypassing the overhead of a traditional CPU entirely. The result classifies handwritten digits in roughly 4 microseconds.

The Approach

The project combined two very different domains. On the software side, a Binarized Neural Network (BNN) was trained in PyTorch — a network where weights and activations are constrained to binary values, dramatically simplifying the arithmetic needed for inference. Binarization is what makes hardware acceleration of this kind practical: instead of full floating-point multiplication, a BNN’s core operations reduce to XNOR and bit-counting (popcount), operations that map naturally and efficiently onto FPGA logic.

On the hardware side, that trained network was implemented as a custom XNOR/Popcount pipeline in Verilog, running directly on a Nexys A7 FPGA. This is where my contribution was concentrated — working through the embedded systems and hardware implementation needed to take a trained model and realize its inference logic as actual digital logic on the board, rather than as software running on a general-purpose processor.

Real-Time Interaction

Beyond the accelerator itself, the team built a real-time web dashboard that communicates with the FPGA board over UART, allowing live interaction with the hardware classifier rather than treating it as a black box running in isolation.

*A short demo of the FPGA-based BNN accelerator in action*

Why This Mattered to Me

This project sits right at the intersection of two things I’m genuinely interested in: machine learning and embedded hardware. Most ML work stops at a trained model running in software — getting hands-on with implementing inference logic directly as digital hardware, and seeing the real speed difference that comes from bypassing a CPU entirely, was a valuable, concrete look at how software and hardware design meet in practice.

Full credit to Harsha Kaushalya for originating and leading this project — it was a great experience contributing to it alongside him and Imal.